1. Field of the Invention
The present invention relates to a data transmission device and an input/output (I/O) interface circuit with a data transmission circuit which enable testing of jitter tolerance upon transmitting or receiving data between LSIs (Large-Scale Integrated Circuits), between a plurality of elements or circuit blocks in an LSI chip, or between printed circuit boards or device housings.
2. Description of the Related Art
In general, data to be transmitted or received between circuit blocks, between chips, or in a device housing includes jitter (phase variations) depending on the service environment such as their transmission line characteristics. To properly identify the data that includes jitter, the data reception circuit is provided with a clock recovery circuit. Many standards set for data transmission and reception define jitter tolerance (resistance to jitter) as the minimum amount of jitter at which the data reception circuit has to correctly identify data. Thus, the jitter tolerance should be inevitably satisfied in the design of data transmission and reception. On the other hand, the jitter tolerance can be measured to thereby evaluate the performance of the data reception circuit.
More specifically, to test a circuit terminating device used in the integrated services digital network, a method for jitter superposition has been disclosed which enables superimposing of a predetermined jitter on an input signal supplied to the circuit terminating device, thereby testing its capability of receiving the signal superimposed with the predefined jitter without any error (e.g., see Patent Document 1). Also disclosed is a packet tester with a delay jitter inserter which can add both a lagging jitter and a leading jitter to a transmitted packet, thereby allowing a delay jitter associated with a nearly actual state of the network to be added to the packet (e.g., see Patent Documents 2 and 3).
However, the jitter tolerance of the aforementioned data transmission/reception circuit cannot be evaluated during its mass production test. This is because the mass production test cannot employ an expensive system from the viewpoint of cost, making it impractical to construct a separate system for generating transmitted/received data that includes the jitter intended by the observer. For example, in the conventional mass production test, the data reception circuit is tested using a loop structure through which data transmitted by the data transmission circuit is directly supplied to the data reception circuit. FIG. 11 is a view illustrating a loop structure for testing the data transmission/reception circuit (the I/O interface circuit).
Referring to FIG. 11, a data transmission/reception circuit 1 includes a data transmission circuit 2 for delivering serial data TXRX_DT, a data reception circuit 3 for receiving the serial data TXRX_DT delivered by the data transmission circuit 2, and a clock generator 4 for delivering a clock signal TX_CK and a clock signal RX_CK to the data transmission circuit 2 and the data reception circuit 3, respectively, based on a reference clock signal REF_CK.
More specifically, the clock generator 4 shown in FIG. 11 delivers the clock signal TX_CK having a frequency of 5 GHz (Gigaherz) to the data transmission circuit 2 as well as the clock signal RX_CK having the same frequency of 5 GHz to the data reception circuit 3, based on the reference clock signal REF_CK having a frequency of 625 MHz (Megahertz). The data transmission circuit 2 and the data reception circuit 3 exchange the serial data TXRX_DT therebetween at a transmission rate of 10 Gbps (bits per second).
Now, the internal configuration of the data transmission circuit 2 will be described below. As shown in FIG. 11, the data transmission circuit 2 includes a clock controller 21, a PRBS (Pseudo Random Bit Sequence) pattern generator 22, selectors 23, 24, a 32:4 converter 25, and a driver circuit 26. The clock controller 21 receives the clock signal TX_CK having a frequency of 5 GHz from the clock generator 4 and then delivers 4-bit 2.5 GHz clock signals TX_DCK having four types of phases, each shifted successively by 90 degrees, to the 32:4 converter 25 and the driver circuit 26.
The 4-bit clock signals TX_DCK are defined as TX_DCK_A, TX_DCK_B, TX_DCK_C, and TX_DCK_D, respectively. The clock controller 21 also frequency divides the clock signal TX_CK by a factor of 16 to deliver the resulting clock signal CLK having a frequency of 312.5 MHz to the PRBS pattern generator 22.
In sync with the clock signal CLK delivered by the clock controller 21, the PRBS pattern generator 22 generates and outputs a pseudo random pattern of 32-bit data PRBS_DT [31:0] for testing the data transmission/reception circuit 1. The PRBS pattern generator 22 is activated when an enable signal PRBS_EN is at a H (high) level. The enable signal PRBS_EN is at a L (low) level when the data transmission/reception circuit 1 operates in a normal mode, but at the H level in a test mode. The PRBS pattern generator 22 will be discussed in detail later.
The selectors 23, 24 switch the signal to be supplied to the 32:4 converter 25 depending on the mode of operation of the data transmission circuit, i.e., between the test and normal modes. More specifically, in the normal mode, the selector 23 selects a clock signal USER_CK externally provided at a given frequency to deliver it to the 32:4 converter 25 as a clock signal TX_ICK. In the test mode, the selector 23 selects a clock signal PRBS_CK supplied by the PRBS pattern generator 22 to deliver it to the 32:4 converter 25 as the clock signal TX_ICK. On the other hand, the selector 24 selects, in the normal mode, arbitrary 32-bit data USER_DT [31:0] provided externally to deliver it as data TX_IDT [31:0] to the 32:4 converter 25. In the test mode, the selector 24 selects the 32-bit data PRBS_DT [31:0] supplied by the PRBS pattern generator 22 to deliver it to the 32:4 converter 25 as the data TX_IDT [31:0].
Then, the 32:4 converter 25 converts the 32-bit data TX_IDT [31:0] received into 4-bit data TX_DT [3:0] to deliver the resulting data to the driver circuit 26. More specifically, the 32:4 converter 25 captures the 32-bit data TX_IDT [31:0] in sync with the clock signal TX_ICK of 312.5 MHz to convert the data in width from 32 bits to 4 bits, and then delivers the resulting 4-bit data TX_DT [3:0] in sync with each of the 4-bit clock signals TX_DCK of 2.5 GHz. The 4-bit data TX_DT [3:0] is defined as TX_DT_A, TX_DT_B, TX_DT_C, and TX_DT_D.
The driver circuit 26 then converts the 4-bit data TX_DT [3:0] to 1-bit serial data TXRX_DT for output. More specifically, the driver circuit 26 uses the 4-bit clock signals TX_DCK having different phases to convert the 4-bit data TX_DT [3:0] to the 1-bit serial data TXRX_DT for output at a transmission rate of 10 Gbps.
Arranged as described above, in the test mode, the data transmission circuit 2 converts the 312.5 Mbps 32-bit data PRBS_DT, generated by the PRBS pattern generator 22 for use with testing, to the 10 Gbps 1-bit serial data TXRX_DT for output.
Now, the internal configuration of the data reception circuit 3 will be described below. As shown in FIG. 11, the data reception circuit 3 includes a clock controller 31, a receiver circuit 32, a 4:32 converter 33, and a pattern comparator 34. The clock controller 31 receives the clock signal RX_CK having a frequency of 5 GHz from the clock generator 4 to deliver 4-bit clock signals RX_DCK having four types of phases, each shifted successively by 90 degrees at a frequency of 2.5 GHz, to the 4:32 converter 33 and the receiver circuit 32. The 4-bit clock signals RX_DCK are defined as RX_DCK_A, RX_DCK_B, RX_DCK_C, and RX_DCK_D, respectively.
The receiver circuit 32 receives the serial data TXRX_DT transmitted by the data transmission circuit 2 to output 4-bit received data RX_DT [3:0] and RX_BDT [3:0]. More specifically, the receiver circuit 32 receives the 10 Gbps 1-bit serial data TXRX_DT at the timing of the 4-bit clock signals RX_DCK having different phases to output the 4-bit 2.5 Gbps received data RX_DT [3:0] and RX_BDT [3:0]. The received data RX_DT [3:0] is provided by capturing each piece of the 1-bit serial data TXRX_DT at a positively receivable timing and converting it into 4-bit data. On the other hand, the received data RX_BDT [3:0] is provided by capturing the serial data TXRX_DT at a point of change in time of each piece thereof and then converting it into 4-bit data.
The 4:32 converter 33 converts the 4-bit received data RX_DT [3:0] and RX_BDT [3:0], supplied by the receiver circuit 32, to 32-bit received data RX_ODT [31:0] and RX_OBDT [31:0] for output. More specifically, the 4:32 converter 33 captures the 2.5 Gbps 4-bit received data RX_DT [3:0] and RX_BDT [3:0] supplied by the receiver circuit 32, in response to the 4-bit clock signals RX_DCK supplied by the clock controller 31, and then converts the captured data to the 312.5 Mbps 32-bit received data RX_ODT [31:0] and RX_OBDT [31:0] for output. The received data RX_ODT [31:0] is supplied to the pattern comparator 34 and a filter 35. On the other hand, the received data RX_OBDT [31:0] is supplied to the filter 35. The 4:32 converter 33 also frequency divides the clock signals RX_DCK of 2.5 GHz by a factor of 8 to create a 312.5 MHz clock signal RX_OCK, which is then delivered to the pattern comparator 34 and the filter 35.
The pattern comparator 34 compares the received data RX_ODT [31:0] delivered by the 4:32 converter 33 with an expectation value, thereby outputting an error flag ERROR serving as a signal for detecting an error upon reception. More specifically, the pattern comparator 34 captures the 32-bit received data RX_ODT [31:0], delivered by the 4:32 converter 33, in sync with the clock signal RX_OCK delivered also by the 4:32 converter 33 to compare the captured data with an expectation value. The pattern comparator 34 is activated when an enable signal COMP_EN is at the H level. The enable signal COMP_EN is at the L level when the data transmission/reception circuit 1 operates in the normal mode, but at the H level in the test mode. The pattern comparator 34 will be discussed in detail later.
The filter 35 outputs a signal PI_CODE for adjusting a phase shift in the clock signals RX_DCK from the clock controller 31 in accordance with the received data RX_ODT [31:0] and RX_OBDT [31:0] delivered by the 4:32 converter 33. For example, when the serial data signal TXRX_DT is being captured at the rising edge of the clock signal RX_DCK, this allows for controlling the operation of the clock controller 31 such that the rising edge of the clock signal RX_DCK lies at the midpoint of change in each serial data signal TXRX_DT (at a timing at which data can be positively captured).
Now, an exemplary conventional circuit configuration of the clock generator 4 shown in FIG. 11 is described below.
FIG. 12 is a view illustrating an exemplary conventional circuit configuration of the clock generator 4 shown in FIG. 11. As shown in FIG. 12, the clock generator 4 includes a phase comparator 41, a filter 42, a VCO (Voltage Controlled Oscillator) 43, a frequency divider 44; and buffers 45, 46. In this arrangement, the phase comparator 41, the filter 42, the VCO 43, and the frequency divider 44 obviously constitute a PLL (Phase Locked Loop), allowing for delivering the clock signals TX_CK and RX_CK, having a frequency of 5 GHz or an eight-fold frequency, with stable phases in accordance with the reference clock signal REF_CK of 625 MHz.
Now, an exemplary conventional circuit configuration of the PRBS pattern generator 22 shown in FIG. 11 will be described below.
FIG. 13 is a view illustrating an exemplary conventional circuit configuration of the PRBS pattern generator 22 shown in FIG. 11. As shown in FIG. 13, the conventional PRBS pattern generator 22 is made up of flip-flops 221, 222, a logic element 223, a flip-flop 224 with an enable function, XOR (exclusive logical sum) circuitry 225, and buffers 226, 227.
The flip-flop 221 latches an external enable signal PRBS_EN at the rising edge of the clock signal CLK and then delivers the resulting signal as a signal START to the input terminal of the flip-flop 222 and a first input terminal of the logic element 223. The flip-flop 222 latches the signal START from the flip-flop 221 at the rising edge of the clock signal CLK and then supplies the resulting signal to a second input terminal of the logic element 223. The logic element 223 delivers a signal START_DET which is AND (logical product) of the signal START supplied to the first input terminal, and the complement of the signal supplied to the second input terminal.
The enable terminal en of the flip-flop 224 with an enable function (hereinafter referred to as the enable FF) 224 is supplied with the signal START_DET delivered by the logic element 223. The enable FF 224 is activated when the signal START_DET changes from the H level to the L level. Additionally, the input terminal of the enable FF 224 is supplied with data DT_NEXT [31:0] delivered by the XOR circuitry 225. Furthermore, the enable FF 224 delivers data DT_NOW [31:0] to the input terminal of the XOR circuitry 225. Still furthermore, the data DT_NOW [31:0] provided by the enable FF 224 is delivered to an external circuit as the data (PRBS pattern) PRBS_DT [31:0] via the buffer 226.
The flip-flops 221, 222 and the enable FF 224 are supplied with the clock signal CLK at their clock terminals. The clock signal CLK is also delivered as the clock signal PRBS_CK via the buffer 227. The flip-flops 221, 222 and the logic element 223 constitutes a rising-edge detector circuit. The rising-edge detector circuit generates the signal START_DET which rises in response to the rising edge of the enable signal PRBS_EN.
The aforementioned arrangement allows the PRBS pattern generator 22 to deliver the PRBS pattern which is generated by the XOR circuitry 225, in response to the rising edge of the enable signal PRBS_EN.
Now, a detailed exemplary circuit configuration of the XOR circuitry 225 shown in FIG. 13 will be explained below. FIG. 14 is a view illustrating a detailed exemplary circuit configuration of the XOR circuitry 225 shown in FIG. 13. As shown in FIG. 14, the XOR circuitry 225 includes XORs (exclusive ORs) 252 to 261, with a 32-bit input terminal 251 and a 32-bit output terminal 262. The input terminal 251 is supplied with the current data DT_NOW [31:0] from the enable FF 224 shown in FIG. 13. This allows the XOR circuitry 225 to generate the next cycle data DT_NEXT [31:0], which is in turn delivered from the output terminal 262. The connection arrangement of the XORs 252 to 261 for connecting between the input terminal 251 and the output terminal 262 is adapted to generate the PRBS pattern. In addition, the aforementioned PRBS pattern, part of which is received by the reception side, thereby allows an expectation value of the subsequently received signal to be generated.
Now, the operation of the PRBS pattern generator 22 shown in FIG. 13 will be explained briefly. FIG. 15 is an explanatory waveform diagram illustrating the operation of the PRBS pattern generator 22 shown in FIG. 13. As shown in FIG. 15, the clock signal CLK is supplied to the PRBS pattern generator 22. First, at time t41, the enable signal PRBS_EN rises. Then, at time t42, the flip-flop 221 latches the enable signal PRBS_EN in sync with the rising edge of the clock signal CLK, thereby allowing the signal START to rise to the H level. This also allows the signal START_DET delivered by the logic element 223 to rise to the H level as well as the enable FF 224 to be inactivated.
Then, at time t43, when the clock signal CLK has risen, the flip-flop 222 changes its output to the H level, causing the signal START_DET delivered by the logic element 223 to fall to the L level. This causes the enable FF 224 to be activated, capture the DT_NEXT [31:0] in sync with the rising edge of the clock signal CLK, and then deliver the captured data as the DT_NOW [31:0]. This allows the buffer 226 to output the DT_NOW [31:0] as the PRBS pattern PRBS_DT [31:0]. As described above, the PRBS pattern generator 22 generates the PRBS pattern PRBS_DT [31:0] in sync with the clock signal CLK for output.
Now, an exemplary conventional circuit configuration of the pattern comparator 34 shown in FIG. 11 will be described below.
FIG. 16 is a view illustrating an exemplary conventional circuit configuration of the pattern comparator 34 shown in FIG. 11. As shown in FIG. 16, the conventional pattern comparator 34 is made up of flip-flops 341, 343, 347 to 349, a selector 342, XOR (exclusive OR) circuitry 344, a comparator 345, a demultiplexer 346, a logic element 350, and a sequencer 351.
The flip-flop 341 captures the data RX_ODT [31:0], supplied by the 4:32 converter 33, at the rising edge of the clock signal RX_OCK to deliver it as data DT [31:0]. The selector 342 selectively outputs the data DT [31:0] delivered by the flip-flop 341 or the data DT_NEXT 2 [31:0] delivered by the XOR circuitry 344 to the flip-flop 343. At this time, the selector 342 performs the aforementioned selection in response to a control signal STATE_SEL from the sequencer 351.
The flip-flop 343 delivers the data, supplied by the selector 342, to the XOR circuitry 344 as data DT_NOW 2 [31:0] in response to the rising edge of the clock signal RX_OCK. The XOR circuitry 344 delivers data DT_NEXT 2 [31:0] in accordance with the data DT_NOW 2 [31:0] supplied by the flip-flop 343. The data DT_NEXT 2 [31:0] delivered by the XOR circuitry 344 is also supplied to the first input terminal of the comparator 345 as expectation value data. The data DT [31:0] delivered by the flip-flop 341 is also supplied to the second input terminal of the comparator 345 as received data.
The comparator 345 compares the expectation value data (data DT_NEXT 2 [31:0]) with the received data (data DT [31:0]) to output the result of the comparison. The comparator 345 outputs the L level if the comparison result exhibits a match, and the H level if it exhibits no match. The demultiplexer 346 delivers the signal, supplied by the comparator 345, to the destination that has been selected in accordance with the control signal STATE_SEL delivered by the sequencer 351. More specifically, the demultiplexer 346 selects the flip-flop 347 as the destination when the control signal STATE_SEL is at the L level, while selecting the sequencer 351 as the destination when the control signal STATE_SEL is at the H level. The flip-flop 347 captures the signal, supplied by the comparator 345 via the demultiplexer 346, at the rising edge of the clock signal RX_OCK to output the error flag ERROR serving as an error detection signal.
The flip-flop 348 latches the enable signal COMP_EN supplied externally in response to the rising edge of the clock signal RX_OCK to output it as the signal START 2 to the input terminal of the flip-flop 349 and the first input terminal of the logic element 350. The flip-flop 349 latches a signal START 2, delivered by the flip-flop 348, at the rising edge of the clock signal RX_OCK to output it to the second input terminal of the logic element 350. The logic element 350 delivers a signal START_DET 2 which is AND of the signal START 2 supplied to the first input terminal, and the complement of the signal supplied to the second input terminal.
The enable terminal en of the sequencer 351 is supplied with the signal START_DET 2 delivered by the logic element 350. Additionally, the input terminal of the sequencer 351 is supplied with a signal CMP_FLAG delivered by the demultiplexer 346. In accordance with the signal START_DET 2, the sequencer 351 also outputs the control signal STATE_SEL which is at the H level for a certain period of time.
The clock terminal of the flip-flops 341, 343, 347 to 349 and the sequencer 351 is supplied with the clock signal RX_OCK. The circuit configuration of the XOR circuitry 344 is the same as the detailed exemplary circuit configuration of the XOR circuitry 225 shown in FIG. 13. The flip-flops 348, 349 and the logic element 350 constitute a rising-edge detector circuit. That is, this rising-edge detector circuit outputs the signal START_DET 2, i.e., a pulsed signal which rises upon detecting the rising edge of the enable signal COMP_EN.
The aforementioned arrangement allows the pattern comparator 34 to compare the received data and the expectation value data to output the error flag ERROR in response to the rising edge of the enable signal COMP_EN.
Now, the operation of the pattern comparator 34 shown in FIG. 16 will be explained briefly. FIG. 17 is an explanatory waveform diagram illustrating the operation of the pattern comparator 34 shown in FIG. 16. As shown in FIG. 17, the clock signal RX_OCK is supplied to the pattern comparator 34. First, at time t51, the enable signal COMP_EN rises. Then, at time t52, the flip-flop 348 latches the enable signal COMP_EN in response to the rising edge of the clock signal RX_OCK, thereby allowing the signal START 2 to rise to the H level. This allows the signal START_DET 2 delivered by the logic element 350 to be at the H level for the duration of one clock.
Then, at time t53, when the signal START_DET 2 has gone through the duration of the H level and fallen to the L level, the sequencer 351 raises the control signal STATE_SEL to the H level. This causes the selector 342 to output the data DT [31:0], delivered by the flip-flop 341, to the flip-flop 343. On the other hand, the demultiplexer 346 delivers the output signal, supplied by the comparator 345, to the sequencer 351 as the signal CMP_FLAG. Thus, the pattern comparator 34 is driven into a LOCK detection state which allows the XOR circuitry 344 to deliver an appropriate expectation value in accordance with received data RX_ODT [31:0].
Now, the LOCK detection state will be explained below. Suppose that patterns are compared at the receiving side. In this case, there are typically two states: the state of detecting the head of received data (LOCK detection state) and the error detection state. The control signal STATE_SEL shown in FIG. 16 provides control to either of the states. More specifically, the STATE_SEL being at the H level corresponds to the LOCK detection state, while the STATE_SEL being at the L level corresponds to the error detection state. During the LOCK detection state, the error flag ERROR is held at the L level.
In the LOCK detection state, the received data DT [31:0] is captured by the flip-flop 343 in every clock cycle and then employed as the initial value data DT_NOW 2 [31:0] for the XOR circuitry 344 to generate the expectation value data DT_NEXT 2 [31:0]. The comparator 345 compares the expectation value data DT_NEXT 2 [31:0] generated as such with the received data DT [31:0]. If the comparison results exhibit matches successively for several cycles in the comparator 345, the process interprets the state as locking (i.e., as being able to generate an appropriate expectation value) and then proceeds to the error detection state. The number of the aforementioned cycles is determined through the processing to be performed by the sequencer 351. More specifically, the sequencer 351 has a function of generating an internal signal HEAD_END, i.e., a pulsed signal which rises after predetermined several cycles have been counted from the falling edge of the signal START_DET 2. Now, referring to FIG. 17, how the process changes to the error detection state will be explained below.
At time t54, the sequencer 351 counts the number of predetermined several cycles, then allowing the internal signal HEAD_END to rise. Then, at time t55, the sequencer 351 causes the internal signal HEAD_END to fall, allowing the control signal STATE_SEL to fall correspondingly. Thus, the pattern comparator 34 is driven into the error detection state, thereby allowing the flip-flop 347 to start delivering the error flag ERROR in sync with the clock signal at time t56.
As described above, the mass production test employs the loop structure in which the transmitted data from the data transmission circuit 2 is directly supplied to the data reception circuit 3 in order to evaluate the transmission and reception function of the data transmission/reception circuit 1.
As described above, the clock controller 31 in the data reception circuit 3 adjusts the phase of the internal clock signal RX_DCK in accordance with the difference in phase between the received data TXRX_DT and the internal clock signal RX_DCK. However, without a change such as 0 to 1 or 1 to 0 in the received data TXRX_DT, it would be impossible to detect the difference between the received data TXRX_DT and the internal clock signal RX_DCK. For this reason, a typical communication standard specifies the length of data having no change as a 0 run length or a 1 run length. That is, the length of a contiguous sequence of data 0 (L level) is defined as a 0 run length, while the length of a contiguous sequence of data 1 (H level) is defined as a 1 run length. For example, the SONET standard defines 72 bits as the maximum length of a 0 run length or a 1 run length. In the data transmission/reception design, it is inevitable to meet jitter tolerance when such data as including a 0 run length or a 1 run length is used.
Prior Arts are disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. Hei 4-220045), Patent Document 2 (Japanese Patent Application Laid-Open No. Hei 1-241945), and Patent Document 3 (Japanese Patent Application Laid-Open No. Hei 1-235437).
However, in the aforementioned mass production test, the transmitted/received data TXRX_DT includes no jitter resulting from the environment in which the data transmission/reception circuit 1 would be used and no jitter corresponding to the jitter tolerance to be specified for the data transmission/reception circuit 1 in its design specifications. In other words, there is a problem of being unable to test jitter tolerance.
Furthermore, the modulation frequency and depth (the amount of modulation) of the jitter imposed on the clock signal need to be combined in a variety of ways to measure the aforementioned jitter tolerance characteristics. This has led to an increasing demand for automatic measurements.
In the aforementioned mass production test, there is also a problem of being unable to evaluate jitter tolerance using transmitted data including a 0 run length or a 1 run length.